~~NOTOC~~
======  Minute of meeting on 2018.02.14 ======

===== 1.  Attendees  =====
-- Alexander Pawlitzki (Thales-Alenia Space, Germany) \\
-- Austin Lesea (Xilinx) \\
-- Barrie Timpe (Xilinx FAE) \\
-- Drew Boudreau (Trident Systems) \\
-- Eliot Glaser (Northrop Grumman) \\
-- Frederick (Eric) Brinlee (Boeing) \\
-- Gary Swift (meeting moderator, Swift ERS) \\
-- George Miclea (Xilinx FAE) \\
-- Hagen Schmidt (Airbus DS, Germany) \\
-- Jeremiah Horner (Northrop Grumman) \\
-- Jim Devereaux (Xilinx FAE) \\
-- Philip Chang (RUAG)\\
-- Ron Smith (Northrop Grumman) \\
-- Scott Arlo Anderson (SEAKR) \\
-- Sebastian Garcia (Slabs) \\
-- Stephen Thomas (Boeing) \\
-- Steve Pearl (General Dynamics) \\
-- Victor Liau (Hughes Network Systems) \\


===== 2.  Topics covered =====

//NOTE: The following are very brief descriptions. Being this a Wiki, please complete/expand/correct them if you think we are missing interesting information (especially regarding anything important for future reference). 
//

Paragraphs below are comments made by Gary (unless otherwise indicated).

Announcement: **Filmetrics' special presentation on die thickness measurement.** To be held on early March. 

Interaction with members regarding **status on porting DUT designs for the Kintex UltraScale (KU060) campaign**.
Steve comments that Boeing has not started yet. 
Gary comment on the ring oscillator design that BYU people is working on. Will be one of the key tests for the latchup suppression experiment, too.
Scott comment that SEAKR neither has started.

**Updated schedule for UltraScale campaign**: fault-injection campaign in April, beam testing in May.

Regarding **additional Virtex-7 testing**, Gary mentions the recent interest of BAE Systems. There's also the MGT data analysis from Boeing tests, still not published.   

**US+ latchup suppression experiment**: Northrop Grumman will be putting additional $12k, probably for buying test boards.
Post- DD electrical performance check has been worked-out this week, besides the ring oscillator design (good indicator of functionality and F_max). The test plan includes monitoring static current, because it's a key TID indicator. We can also use a standard IBERT test on the MGTs. 
Looking for volunteers contributing engineering time for the designs development.
Some of the more sophisticated parametric testing would be appropriate to do running the parts in a full VLSI tester. This could be deferred after the success of the demo experiment.

Spinoff telecon meeting for the US+ latchup suppression experiment: Tuesdays 11:30 PST.


**Virtex-7 data analysis** (2017 campaign): Two main updates:

1. This week Boeing updated the **PLL/MMCM analysis.** 
Seems that FuncMon has logged events faster in some runs, this is strange. 
Now we have a histogram of the length of time for event occurrences. We were expecting 2 distributions overlapped: one for short transients, other for longer outages (e.g., state machines or feedback loops getting confused). And those on top of a background for CRAM upsets (fixed by the scrubber). 
We are seeing the background from the scrubber is particularly low (may be OK, because of the low number of CRAM bits involved), then only one of the two distributions; probably filtering-out the short transients. 
The idea is to apply this analysis method in the V-5QV data.

2. **Thickness & LET assignment**. 
Gary shows the recent measurements performed by Filmetrics with their interferometric IR machine. 


**Test infrastructure (HW) status**. Gen-4 motherboard and KU060 DUT board. Sandia is also working on a KU060 DUT card, interfacing both with std. eval. boards and with the motherboard/backplane.
Looking to complete a first order of boards, to settle down the price. 

**Annual Meeting date**. Near end of August, Monday/Tuesday. 


Round table.


Austin comments on the **ring oscillator design used in Xilinx tests**. 
What Pierre Maillard presented on past week is a //commercial// qualification test. This is done to ensure proper working of the part after several passes through an X-ray AOI machine, giving a certain total dose, during board rework procedures.
Gary asks about the maximum achievable frequency of a ring oscillator implemented in the FPGA fabric.
Austin: What we use for a "ring oscillator" is probably the farthest you could imagine; it's 7 stages of LUTs and involves some F/Fs. We want the ring oscillator to tell us the propagation of the rising edge vs. the propagation of the falling edge. So, we have rising edge rings and falling edge rings. Sorta' standard thing we use. We can get like heatmaps of rising edge vs. falling edge.
Verilog code available to the XRTC.

Drew Boudreau introduces himself. He is a principal systems engineer at Trident Systems; V-5 SpaceVPX xver cards, SDR market. Interested in the ZUS+ for Space. Currently developing a ZU19-based card, available in April. 

Eliot (NG) mentions interesting tests for the ZUS+ latchup suppression experiment: DDR I/F and IOBs. 
Gary also mentions testing the ADC and SysMon blocks.

George Miclea introduces himself. He is a Xilinx FAE in Southern CA, working for Avnet, covering accounts like JPL.

Steve Thomas asks about the required gen-4 boards for the upcoming tests. 
Gary explains that the "motherboard" is the backplane, then there's 2 identical "DUT boards" plugged in, one is the actual DUT card, and the other corresponds to FuncMon. There's also a small board required to be plugged in the FMC connector of the latter, as an adapter to the usual FuncMon's ribbon cable. 
Alternatively, old boards could be used as FuncMon.































